Traps, 1 processor states, normal and special traps, Traps 35 – FUJITSU Implementation Supplement Fujitsu SPARC64 V User Manual

Page 46: Processor states, normal and special traps 35

Advertising
background image

35

F. C H A P T E R

7

Traps

Please refer to Chapter 7 of Commonality. Section numbers in this chapter
correspond to those in Chapter 7 of Commonality.

This chapter adds SPARC64 V-specific information in the following sections:

Processor States, Normal and Special Traps on page 35

RED_state on page 36

error_state on page 36

Trap Categories on page 37

Deferred Traps on page 37

Reset Traps on page 37

Uses of the Trap Categories on page 37

Trap Control on page 38

PIL Control on page 38

Trap-Table Entry Addresses on page 38

Trap Type (TT) on page 38

Details of Supported Traps on page 39

Exception and Interrupt Descriptions on page 39

7.1

Processor States, Normal and Special
Traps

Please refer to Section 7.1 of Commonality.

Advertising