FUJITSU Implementation Supplement Fujitsu SPARC64 V - Manual (Page 83)

72 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
32 Deferred traps
SPARC64 V signals a deferred trap in a few of its severe error conditions.
SPARC64 V does not contain a deferred trap queue. 37, 149
33 Trap precision
There are no deferred traps in
SPARC64 V other than the trap caused by a
few severe error conditions. All traps that occur as the result of program
execution are precise.
37
34 Interrupt clearing
For details of interrupt handling see Appendix N, Interrupt Handling. —
35 Implementation-dependent traps
SPARC64 V supports the following traps that are implementation
dependent:
• interrupt_vector_trap ( tt = 060
16
)
• PA_watchpoint ( tt = 061
16
)
• VA_watchpoint ( tt = 062
16
)
• ECC_error ( tt = 063
16
)
• fast_instruction_access_MMU_miss ( tt = 064
16
through 067
16
)
• fast_data_access_MMU_miss ( tt = 068
16
through 06B
16
)
• fast_data_access_protection ( tt = 06C
16
through 06F
16
)
• async_data_error ( tt = 040
16
)
39, 39
36 Trap priorities
SPARC64 V ’s implementation-dependent traps have the following
priorities:
• interrupt_vector_trap (priority = 16)
• PA_watchpoint (priority= 12)
• VA_watchpoint (priority= 1)
• ECC_error (priority = 33)
• fast_instruction_access_MMU_miss (priority = 2)
• fast_data_access_MMU_miss (priority = 12)
• fast_data_access_protection (priority = 12)
• async_data_error (priority = 2)
38
37 Reset trap
SPARC64 V implements power-on reset (POR) and watchdog reset.
37
38 Effect of reset trap on implementation-dependent registers
See Section O.3, Processor State after Reset and in RED_state, on page 141. 141
39 Entering error_state on implementation-dependent errors
CPU watchdog timeout at 2 33 ticks, a normal trap, or an SIR at TL = MAXTL
causes the CPU to enter error_state .
36
40 Error_state processor state
SPARC64 V optionally takes a watchdog reset trap after entry to
error_state . Most error-logging register state will be preserved. (See also
impl. dep. #254.)
36
41 Reserved.
TABLE C-1 SPARC64 V Implementation Dependencies (3 of 11)
Nbr SPARC64 V Implementation Notes Page