9 version (ver) register, 11 ancillary state registers (asrs), Performance control register (pcr) (asr 16) – FUJITSU Implementation Supplement Fujitsu SPARC64 V User Manual
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SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Note –
Spurious setting of the
PSTATE.RED
bit by privileged software should not
be performed, since it will take the SPARC64 V into
RED_state
without the
required sequencing.
5.2.9
Version (VER) Register
shows the values for the
VER
register for SPARC64 V.
The
manuf
field contains Fujitsu’s 8-bit JEDEC code in the lower 8 bits and zeroes in
the upper 8 bits. The
manuf
,
impl
, and
mask
fields are implemented so that they
may change in future SPARC64 V processor versions. The
mask
field is incremented
by 1 any time a programmer-visible revision is made to the processor. See the
SPARC64 V Data Sheet to determine the current setting of the
mask
field.
5.2.11
Ancillary State Registers (ASRs)
Please refer to Section 5.2.11 of Commonality for details of the ASRs.
Performance Control Register (PCR) (ASR 16)
SPARC64 V implements the
PCR
register as described in SPARC JPS1 Commonality,
with additional features as described in this section.
In SPARC64 V, the accessibility of
PCR
when
PSTATE.PRIV
= 0 is determined by
PCR.PRIV
. If
PSTATE.PRIV
= 0 and
PCR.PRIV
= 1, an attempt to execute either
RDPCR
or
WRPCR
will cause a
privileged_action
exception. If
PSTATE.PRIV
= 0 and
PCR.PRIV
= 0,
RDPCR
operates without privilege violation and
WRPCR
causes a
privileged_action
exception only when an attempt is made to change (that is, write 1
to)
PCR.PRIV
(impl. dep. #250).
See Appendix Q, Performance Instrumentation, for a detailed discussion of the
PCR
and
PIC
register usage and event count definitions.
TABLE 5-1
VER
Register Encodings
Bits
Field
Value
63:48
manuf
0004
16
(impl. dep. #104)
47:32
impl
5 (impl. dep. #13)
31:24
mask
n (The value of n depends on the processor chip version)
15:8
maxtl
5
4:0
maxwin
7