Mocomtech CDM-QX - Manual (Page 92)

CDM-Qx/QxL Multi-Channel Satellite Modem with DoubleTalk™ Carrier-in-Carrier® Revision 7
Front Panel Operation MN/CDMQX.IOM
5–26
5.4.3.8 CONFIG: Rx
Æ Buf
Rx Buffer: Internal Rx-Sat
Tx-Terr Ins External (◄ ►,ENT)
To set the Receive Buffer Clock Source, select Internal, Rx-Sat, Tx-Terr, Ins, or External
using the ◄ ► arrow keys. Press
ENTER
when done.
Note: Tx-Terrestrial will only be selected if the modules are grouped as a modem. Selecting
either one will allow the user to select the buffer size as shown below (also, note that External
will only be selected if QDI interface type is selected):
Rx Buffer Size
Disabled (S T,ENT)
Values of Disabled, ±512, 1024, 2048, 4096, 8192, and 16384 bits are possible. Edit the size, in
bits, of the Plesiochronous/Doppler Buffer by changing the value using the S T arrow keys.
then pressing
ENTER
.
Note that, for QDI interface type, the selectable Rx Buffer settings are Rx-Sat, Tx_Terr and
External:
• Tx-Terr is a recovered E1 clock from the Tx terrestrial E1 data. This setting will also
loop the Tx terrestrial E1 data to the Rx terrestrial E1 data port. The incoming Rx IF data
will be instered and overwrite this “looped” data.
• External is a user-provided E1 frequency balanced clock on J5 of the Quad E1 interface
card.
When Disabled is selected, the Plesiochronous/Doppler buffer is disabled. The receive clock will
then be derived from the satellite signal, and will therefore be subject to clock offsets relative to the
local transmit clock, This is due in part to the originating clock being slightly different from the
local clock (a so-called plesiochronous offset), and to the motion of the satellite (a Doppler offset).
The input to the buffer will be the signal from the satellite, with any clock offsets and jitter. The
output from the buffer will be derived from the local TRANSMIT clock. In this way, the receive
data will be perfectly synchronous with this local clock.
The modem operates with independent receive and transmit data rates. Even in this configuration,
where RX data rate <> TX data rate, the output clock for the buffer will be phase locked to the
transmit clock.
While it is only possible to select the size in bits, the corresponding total buffer size is displayed
in ms (which will vary in inverse proportion to the data rate).