Agilent Technologies L4400 - Manual (Page 79)

Operating and Programming 3
L4400 User’s Guide 67
The lightning- caused transient overvoltages that may occasionally occur
on mains power outlets may be as high as 2500 Vpeak.

High Energy Sources
The Analog Buses are designed to handle inputs up to their rated
currents or their rated powers, whichever is less. Under certain fault
conditions, high energy sources could provide substantially more current
or power than the instrument can handle. It is important to provide
external current limiting, such as fuses, if the inputs are connected to
high- energy sources.

Safety Interlock
The Safety Interlock feature prevents connections to the Analog Buses

if no terminal block or properly- wired cable is connected to the L4421A
or L4433A.
Normally, if you attempt to connect to the Analog Buses without a
terminal block or properly- wired cable connected, an error is generated.
You can, however, temporarily disable errors generated by the Safety
Interlock feature. This simulation mode may be useful during test system
development when you may not have connected any terminal blocks or
cables to your module.

• When the simulation mode is enabled, the Analog Bus relays will
appear to close and open as directed. For example, no errors are
generated if you close an Analog Bus relay from the remote interface
or Web Interface. However, remember that the Safety Interlock feature
prevents the actual hardware state of the Analog Bus relays from
being changed. When you connect a terminal block or cable to the
module, the Analog Bus relays will open and close normally.
WA R N I N G
Do not connect the Analog Buses directly to a mains power outlet.

If it is necessary to measure a mains voltage or any circuit where a

large inductive load may be switched, you must add signal
conditioning elements to reduce the potential transients before they
reach the Analog Buses.
C A U T I O N
Install current limiting devices between high energy sources and the
module inputs.
C A U T I O N
The Safety Interlock feature is implemented in hardware on the modules
and cannot be circumvented. Regardless of whether the simulation mode
is enabled or disabled, all Analog Bus operations are prohibited as long as
no terminal block or properly-wired cable is connected to the module.