Brocade FastIron SX, FCX, and ICX Diagnostic Reference - Manual (Page 33)

Brocade FastIron SX, FCX, and ICX Diagnostic Reference 21
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MSTP debug commands
3
If the MSTP level 3 is enabled, an output similar to the following is displayed.
Brocade# debug mstp level 3
Brocade# [ebf4d] MSTP_RX[pid=#0] ***
cist_Rx[ebf4d] CIST, Port(#0)
[ebf4d] MSTP_RX[pid=#0] done (region) ***
[ebf4d] MSTP_RX[pid=#1] ***
cist_Rx[ebf4d] CIST, Port(#1)
[ebf4d] MSTP_RX[pid=#1] done (region) ***
[ebf61] MSTP_RX[pid=#0] ***
cist_Rx[ebf61] CIST, Port(#0)
[ebf61] MSTP_RX[pid=#0] done (region) ***
[ebf61] MSTP_RX[pid=#1] ***
cist_Rx[ebf61] CIST, Port(#1)
[ebf61] MSTP_RX[pid=#1] done (region) ***
n[ebf75] MSTP_RX[pid=#0] ***
cist_Rx[ebf75] CIST, Port(#0)
[ebf75] MSTP_RX[pid=#0] done (region) ***
[ebf75] MSTP_RX[pid=#1] ***
cist_Rx[ebf75] CIST, Port(#1)
[ebf75] MSTP_RX[pid=#1] done (region) ***
debug mstp msti
Syntax: [no] debug mstp msti decimal
This command displays information for a specific MSTP instance. The decimal variable specifies
the value 0 for CIST and from 1 through 4094 for the Multiple Spanning Tree Instance (MSTI).
Brocade# debug mstp msti 0
MSTP debugging turned on for instances 0
If this command is enabled, an output similar to the following is displayed.
Brocade# debug mstp msti 2
MSTP debugging turned on for instances 2 ,0
Brocade# debug mstp enable
Brocade# debug mstp events
MSTP Event debugging ON
Brocade# MSTP[0x175f15]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/1
MSTP[0x175f15]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/2
MSTP[0x175f21]: PRX RECEIVE->RECEIVE - Port 1/1/1
MSTP[0x175f21]: PIM CURRENT->RECEIVE - MST 0, Port 1/1/1
MSTP[0x175f21]: PIM RECEIVE->REPEATED_DESIGNATED - MST 0, Port 1/1/1
MSTP: mstp_updtRcvdInfoWhileCist mst=0, Port 1/1/1, rcvdInfoWhile 5->7
MSTP[0x175f21]: PIM CURRENT->RECEIVE - MST 2, Port 1/1/1
MSTP[0x175f21]: PIM RECEIVE->REPEATED_DESIGNATED - MST 2, Port 1/1/1
MSTP: mstp_updtRcvdInfoWhileMsti mst=2, Port 1/1/1, rcvdInfoWhile 4->7
MSTP[0x175f21]: PRX RECEIVE->RECEIVE - Port 1/1/2
MSTP[0x175f21]: PIM CURRENT->RECEIVE - MST 0, Port 1/1/2
MSTP[0x175f21]: PIM RECEIVE->REPEATED_DESIGNATED - MST 0, Port 1/1/2
MSTP: mstp_updtRcvdInfoWhileCist mst=0, Port 1/1/2, rcvdInfoWhile 5->7
MSTP[0x175f21]: PIM CURRENT->RECEIVE - MST 2, Port 1/1/2
MSTP[0x175f21]: PIM RECEIVE->REPEATED_DESIGNATED - MST 2, Port 1/1/2
MSTP: mstp_updtRcvdInfoWhileMsti mst=2, Port 1/1/2, rcvdInfoWhile 4->7
MSTP[0x175f29]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/1
MSTP[0x175f29]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/2
noMSTP[0x175f35]: PRX RECEIVE->RECEIVE - Port 1/1/1
MSTP[0x175f35]: PIM CURRENT->RECEIVE - MST 0, Port 1/1/1