Altera MAX 10 Embedded Memory - Manual (Page 20)

Figure 3-4: Mixed-Port Read-During-Write: Old Data Mode
a b
a (old data) b (old data)
clk_a&b
wren_a
address_a
q_b (asynch)
rden_b
a b address_b
data_a A B C D E F
A B D E
In Don't Care mode, the old data is replaced with “Don't Care”.
Mixed-Port Read-During-Write Operation with Dual Clocks
For mixed-port read-during-write operation with dual clocks, the relationship between the clocks
determines the output behavior of the memory.
If You... ...Then
Use the same clock for the two clocks The output is the old data from the address
location.
Use different clocks The output is unknown during the mixed-port
read-during-write operation. This unknown value
may be the old or new data at the address location,
depending on whether the read happens before or
after the write.
3-4 Mixed-Port Read-During-Write Operation with Dual Clocks
UG-M10MEMORY
2015.05.04
Altera Corporation MAX 10 Embedded Memory Design Consideration
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