Altera MAX 10 Embedded Memory - Manual (Page 31)

Figure 5-4: RAM: 2-Port IP Core Signals with the Two Read/Write Ports and Single Clock Options
Enabled
data_a[]
wren_a
data_b[]
address_b[]
addressstall_a
clock
enable
q_a[]
aclr
address_a[]
wren_b
addressstall_b
rden_a
rden_b
byteena_a[]
q_b[]
UG-M10MEMORY
2015.05.04
RAM: 2-PORT IP Core References 5-3
RAM: 2-PORT IP Core References Altera Corporation
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