Altera MAX 10 Embedded Memory - Manual (Page 32)

Figure 5-5: RAM: 2-Port IP Core Signals with the Two Read/Write Ports and Dual Clock: Use Separate
'Input' and 'Output' Clocks Options Enabled
data_a[]
wren_a
data_b[]
address_b[]
addressstall_a
inclock
inclocken
outclock
outclocken
q_a[]
out_aclr
address_a[]
wren_b
addressstall_b
rden_a
rden_b
byteena_a[]
q_b[]
5-4 RAM: 2-PORT IP Core References
UG-M10MEMORY
2015.05.04
Altera Corporation RAM: 2-PORT IP Core References
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