Altera Transceiver PHY IP Core - Manual (Page 242)

Signal Name Direction Description
phy_mgmt_readdata[31:0]
Output Output data.
phy_mgmt_write
Input Write signal.
phy_mgmt_read
Input Read signal.
phy_mgmt_waitrequest
Output When asserted, indicates that the
Avalon-MM slave interface is unable
to respond to a read or write request.
When asserted, control signals to the
Avalon-MM slave interface must
remain constant.
Custom PHY IP Core Registers
This topic specifies the registers that you can access over the PHY management interface using word
addresses and a 32-bit embedded processor. A single address space provides access to all registers.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
PMA Common Control and Status Registers
Table 9-21: PMA Common Control and Status Registers
Word
Addr
Bits R/W Register Name Description
0x022 [31:0] R
pma_tx_pll_is_locked
Bit[P] indicates that the TX/CMU PLL (P)
is locked to the input reference clock.
There is typically one
pma_tx_pll_is_
locked
bit per system.
Reset Control Registers–Automatic Reset Controller
Table 9-22: Reset Control Registers–Automatic Reset Controller
Word
Addr
Bits R/W Register Name Description
0x041 [31:0] RW
reset_ch_bitmask
Reset controller channel bit mask for reset
registers at 0x042 and 0x044. The default
value is all 1s. Channel
<n>
can be reset
when bit
<n>
= 1.
UG-01080
2015.01.19
Custom PHY IP Core Registers 9-29
Custom PHY IP Core Altera Corporation
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