Altera Transceiver PHY IP Core - Manual (Page 441)

Table 14-23: General and Datapath Parameters
Parameter Range Description
10G PCS protocol mode
basic
interlaken
sfi5
teng_baser
teng_sdi
Specifies the protocol that you intend to
implement with the Native PHY. The
protocol mode selected guides the
MegaWizard in identifying legal settings
for the 10G PCS datapath. Use the
following guidelines to select a protocol
mode:
• basic : Select this mode for when
none of the other options are
appropriate. You should also select
this mode to enable diagnostics, such
as loopback.
• interlaken: Select this mode if you
intend to implement Interlaken.
• sfi5 : Select this mode if you intend
to implement the SERDES Framer
Interface Level 5 protocol.
• teng_baser : select this mode if you
intend to implement the 10GBASE-R
protocol.
• teng_sdi : 10G SDI
10G PCS/PMA interface width 32, 40, 64 Specifies the width of the datapath that
connects the FPGA fabric to the PMA.
FPGA fabric/10G PCS interface width
32
40
50
64
66
67
Specifies the FPGA fabric to TX PCS
interface width .
The 66-bit FPGA fabric/PCS interface
width is achieved using 64-bits from the
TX and RX parallel data and the lower
2-bits from the control bus.
The 67-bit FPGA fabric/PCS interface
width is achieved using the 64-bits from
the TX and RX parallel data and the
lower 3-bits from the control bus.
10G TX FIFO
The TX FIFO is the interface between TX data from the FPGA fabric and the PCS. This FIFO is an
asynchronous 73-bit wide, 32-deep memory buffer It also provides full, empty, partially full, and empty
flags based on programmable thresholds. The following table describes the 10G TX FIFO parameters.
14-30 10G PCS Parameters for Arria V GZ Native PHY
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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