Reconfiguration management interface, Reconfiguration management interface -10 – Altera Transceiver PHY IP Core User Manual
Page 527
Signal Name
Direction
Description
tx_cal_busy
Output
This optional signal is asserted while initial TX calibra‐
tion is in progress and no further reconfiguration
operations should be performed. It is also asserted if
reconfiguration controller is reset. It will not be asserted
if you manually re-trigger the calibration IP. You can
monitor this signal to determine the status of the
Transceiver Reconfiguration Controller. Arria V devices
require DCD calibration for channels with data rates
equal to or greater than 4.9152 Gbps.
In Arria V devices, you cannot run DCD calibration for
multiple channels on the same side of a device simulta‐
neously. If your design includes more than 1 Transceiver
Reconfiguration Controller on a single side of the
FPGA, you must daisy chain the
tx_cal_busy
output
port to the next
cal_busy_in
input port on the same
side of the FPGA.
rx_cal_busy
Output
This optional signal is asserted while initial RX calibra‐
tion is in progress and no further reconfiguration
operations should be performed. It is also asserted if
reconfiguration controller is reset. It will not be asserted
if you manually re-trigger the calibration IP. You can
monitor this signal to determine the status of the
Transceiver Reconfiguration Controller.
Reconfiguration Management Interface
This section describes the reconfiguration management interface.
The reconfiguration management interface is an Avalon-MM slave interface. You can use an embedded
controller to drive this interface. Alternatively, you can use a finite state machine to control all Avalon-
MM reads and writes to the Transceiver Reconfiguration Controller. This interface provides access to the
Transceiver Reconfiguration Controller’s Avalon-MM registers.
For more information about the Avalon-MM protocol, including timing diagrams, refer to the Avalon
Interface Specifications.
16-10
Reconfiguration Management Interface
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview