Altera Transceiver PHY IP Core - Manual (Page 550)

Channel Reconfiguration
If you turn on Enable channel/PLL reconfiguration in the Transceiver Reconfiguration Controller GUI,
you can change the following channel settings:
• TX PMA settings
• RX PMA settings
• RX CDR input clock
• Reference clock inputs
• FPGA fabric transceiver width
When you select Enable Channel Interface, in the Custom, Low Latency, Deterministic Latency
Transceiver PHY GUIs, the default width of the FPGA fabric to transceiver interface increases for both
the Standard and 10G datapaths as follows:
• Standard datapath—The TX interface is 44 bits. The RX interface is 64 bits.
• 10G datapath— TX only, RX only, and duplex channels are all 64 bits.
However, depending upon the FPGA fabric transceiver width specified, only a subset of the 64 bits may
carry valid data. Specifically, in the wider bus, only the lower <n> bits are used, where <n> is equal to the
width of the FPGA fabric width specified in the transceiver PHY IP core. The following table illustrates
this point for the 10G datapath, showing three examples where the FPGA fabric interface width is less
than 64 bits.
Table 16-23: Channel Reconfiguration Bit Ordering
Number of Lanes Specified FPGA
Fabric Width (Total
Bits)
Default Channel
Width (Total Bits)
Used Bits
1 32 bits (32 bits) 64 bits/lane (64 bits) Lane 0: [31:0]
2 40 bits (80 bits) 64 bits/lane (128
bits)
Lane 0: [39:0]
Lane 1: [103:64]
3 40 bits (120 bits) 64 bits/lane (192
bits)
Lane 0: [39:0]
Lane 1: [103:64]
Lane 2: [167:128]
PLL Reconfiguration
If you turn on Enable PLL reconfiguration support block in the Transceiver Reconfiguration Controller
GUI, you can change the following channel settings:
• TX PLL settings
• TX PLL selection
Note: When you specify multiple PLLs, you must use the QSF assignment,
XCVR_TX_PLL_RECONFIG_GROUP
, to identify the PLLs within a reconfiguration group. The
XCVR_TX_PLL_RECONFIG_GROUP
assignment identifies PLLs that the Quartus II Fitter can merge.
UG-01080
2015.01.19
Channel Reconfiguration 16-33
Transceiver Reconfiguration Controller IP Core Overview Altera Corporation
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