Altera Transceiver PHY IP Core - Manual (Page 39)

Signal Name Direction Description
xgmii_tx_dc_[<n>71:0]
Input Contains 8 lanes of data and control for
XGMII. Each lane consists of 8 bits of data and
1 bit of control.
• Lane 0-[7:0]/[8]
• Lane 1-[16:9]/[17]
• Lane 2-[25:18]/[26]
• Lane 3-[34:27]/[35]
• Lane 4-[43:36]/[44]
• Lane 5-[52:45]/[53]
• Lane 6-[61:54]/[62]
• Lane 7-[70:63]/[71]
Refer to
Table 3-11 for the mapping of the
xgmii_tx_dc
data and control to the
xgmii_
sdr_data
and
xgmii_sdr_ctrl
signals.
tx_ready
Output Asserted when the TX channel is ready to
transmit data. Because the
readyLatency
on
this Avalon-ST interface is 0, the MAC may
drive
tx_ready
as soon as it comes out of reset.
xgmii_tx_clk
Input The XGMII TX clock which runs at 156.25
MHz. Connect
xgmii_tx_clk
to
xgmii_rx_
clk
to guarantee this clock is within 150 ppm
of the transceiver reference clock.
XGMII RX Interface
xgmii_rx_dc_<n>[71:0]
Output Contains 8 lanes of data and control for
XGMII. Each lane consists of 8 bits of data and
1 bit of control.
• Lane 0-[7:0]/[8]
• Lane 1-[16:9]/[17]
• Lane 2-[25:18]/[26]
• Lane 3-[34:27]/[35]
• Lane 4-[43:36]/[44]
• Lane 5-[52:45]/[53]
• Lane 6-[61:54]/[62]
• Lane 7-[70:63]/[71]
Refer to
Table 3-12 for the mapping of the
xgmii_rx_dc
data and control to the
xgmii_
sdr_data
and
xgmii_sdr_ctrl
signals.
rx_ready
Output Asserted when the RX reset is complete.
UG-01080
2015.01.19
10GBASE-R PHY Data Interfaces 3-15
10GBASE-R PHY IP Core Altera Corporation
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