Altera Transceiver PHY IP Core - Manual (Page 262)

Optional Status Interface
The following table describes the signals that comprise the optional status interface:
Table 10-9: Optional Status Interface
Signal Name Direction Description
rx_is_lockedtodata[<n>-1:0]
Output When asserted, indicates that the RX CDR is
locked to incoming data. This signal is optional.
If latency is not critical, you can read the value of
this signal from the
Rx_is_lockedtodata
register.
rx_is_lockedtoref[<n>-1:0]
Output When asserted, indicates that the RX CDR is
locked to the input reference clock. This signal is
optional. When the RX CDR is locked to data,
you can ignore transitions on this signal. If
latency is not critical, you can read the value of
this signal from the
rx_is_lockedtoref
register.
pll_locked[<n>-1:0]
Output When asserted, indicates that the TX PLL is
locked to the input reference clock. This signal is
asynchronous.
tx_bitslip[<n>-1:0]
Input When set, the data sent to the PMA is slipped.
The maximum number of bits that can be slipped
is equal to the value selected in the serialization
factor field - 1 or <d> -1.
rx_bitslip[<n>-1:0]
Input When set, the RX word aligner operates in bit
slip mode.
Low Latency PHY Clock Interface
The following table describes reference clock for the Low Latency PHY. The input reference clock,
pll_ref_clk
, drives a PLL inside the PHY-layer block, and a PLL output clock,
rx_clkout
is used for all
data, command, and status inputs and outputs.
Table 10-10: Clock Signals
Signal Name Direction Description
tx_coreclkin[<n>-1:0]
Input This is an optional clock to drive the write
side of the TX FIFO.
rx_coreclkin[<n>-1:0]
Input This is an optional clock to drive the read
side of the RX FIFO.
UG-01080
2015.01.19
Optional Status Interface 10-15
Low Latency PHY IP Core Altera Corporation
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