Altera Transceiver PHY IP Core - Manual (Page 654)

ALTGX Parameter Name (Default Value) CI Express PHY (PIPE)
Parameter Name
Comments
Train receiver CDR from pll_inclk (false)
Not available in
MegaWizard Interface
Use assignment editor
to make these
assignments
TX PLL bandwidth mode (Auto)
RX CDR bandwidth mode (Auto)
Acceptable PPM threshold (±300)
Analog Power(VCCA_L/R) (Auto)
Reverse loopback option (No loopback)
Enable static equalizer control (false)
DC gain (1)
RX Vcm (0.82)
Force signal detection (Off)
Signal Detect threshold (4)
Use external receiver termination (Off)
RX term (100)
Transmitter buffer power(VCCH) (1.5)
TX Vcm (0.65)
Use external transmitter termination (Off)
TX Rterm (100)
VCO control setting (5)
Pre-emphasis 1st post tap (18)
Not available in
MegaWizard Interface
Use assignment editor
to make these
assignments
Pre-tap (0)
2nd post tap (0)
DPRIO - VOD, Pre-em, Eq and EyeQ (Off)
DPRIO - Channel and TX PLL Reconfig (Off)
Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV
and Stratix V Devices
This section lists the differences between the top-level signals in Stratix IV GX and Stratix V GX/GS
devices. PIPE standard ports remain, but are now prefixed with pipe_. Clocking options are simplified to
match the PIPE 2.0 specification.
20-8 Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V
Devices
UG-01080
2013.12.20
Altera Corporation Migrating from Stratix IV to Stratix V Devices Overview
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