Altera Transceiver PHY IP Core - Manual (Page 422)

Parameter Range Description
Enable rx_set_lockedtodata
and rx_set_locktoref ports
On/Off When you turn this option On, the
rx_set_lockedt-
data
and rx_set_lockedtoref ports are outputs of the
PMA.
Enable rx_pma_bitslip_port On/Off When you turn this option On, the
rx_pma_bitslip
is an input to the core. The deserializer slips one clock
edge each time this signal is asserted. You can use this
feature to minimize uncertainty in the serialization
process as required by protocols that require a
datapath with deterministic latency such as CPRI.
Enable rx_seriallpbken port On/Off When you turn this option On, the
rx_seriallpbken
is an input to the core. When your drive a 1 on this
input port, the PMA operates in loopback mode with
TX data looped back to the RX channel.
The following table lists the best case latency for the most significant bit of a word for the RX deserializer
for the PMA Direct datapath. For example, for an 8-bit interface width, the latencies in UI are 11 for bit 7,
12 for bit 6, 13 for bit 5, and so on.
Table 14-8: Latency for RX Deserialization in Arria V GZ Devices
FPGA Fabric Interface Width Arria V GZ Latency in UI
8 bits 11
10 bits 13
16 bits 19
20 bits 23
32 bits 35
40 bits 43
64 bits 99
80 bits 123
Table 14-9: Latency for TX Serialization in Arria V GZ Devices
The following table lists the best- case latency for the LSB of the TX serializer for all supported interface widths for
the PMA Direct datapath.
FPGA Fabric Interface Width Arria V GZ Latency in UI
8 bits 44
10 bits 54
16 bits 68
20 bits 84
32 bits 100
40 bits 124
64 bits 132
UG-01080
2015.01.19
PMA Parameters for Arria V GZ Native PHY 14-11
Arria V GZ Transceiver Native PHY IP Core Altera Corporation
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