Altera Transceiver PHY IP Core - Manual (Page 300)

Figure 12-1: Stratix V Native Transceiver PHY IP Core
PLLs
PMA
altera _xcvr_native_ <dev>
Transceiver Native PHY
Transceiver
Reconfiguration
Controller
Reconfiguration to XCVR
Reconfiguration from XCVR
TX and RX Resets
Calilbration Busy
PLL and RX Locked
RX PCS Parallel Data
TX PCS Parallel Data
CDR Reference Clock
(when neither PCS is enabled)
TX PLL Reference Clock
Serializer/
Clock
Generation
Block
RX Serial Data
to
FPGA fabric
Transceiver
PHY Reset
Controller
TX PMA Parallel Data
RX PMA Parallel Data
TX Serial Data
Serializer
Deserializer
Standard
PCS
(optional)
10G PCS
(optional)
In a typical design, the separately instantiated Transceiver PHY Reset Controller drives reset signals to
Native PHY and receives calibration and locked status signal from the Native PHY. The Native PHY
reconfiguration buses connect the external Transceiver Reconfiguration Controller for calibration and
dynamic reconfiguration of the PLLs.
You specify the initial configuration when you parameterize the IP core. The Transceiver Native PHY IP
Core connects to the Transceiver Reconfiguration Controller IP Core to dynamically change reference
clocks and PLL connectivity at runtime.
Device Family Support for Stratix V Native PHY
This section describes the device family support available in the Stratix V native PHY.
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 12-1: Device Family Support
This tables lists the level of support offered by the Stratix V Transceiver Native PHY IP Core for Altera device
families.
Device Family Support
Stratix V devices Final
Other device families No support
12-2 Device Family Support for Stratix V Native PHY
UG-01080
2015.01.19
Altera Corporation Stratix V Transceiver Native PHY IP Core
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