Altera Transceiver PHY IP Core User Manual
Page 507
Name
Direction
Description
pll_powerdown[<p>-1:0]
Input
When asserted, resets the TX PLL. Active
high, edge sensitive reset signal. By
default, the Cyclone Native Transceiver
PHY IP Core create a separate
pll_
powerdown
signal for each logical PLL.
However, the Fitter may merge the PLLs
if they are in the same transceiver bank.
PLLs can only be merged if their
pll_
powerdown
signals are driven from the
same source. If the PLLs are in separate
transceiver banks, you can choose to
drive the
pll_powerdown
signals
separately.
tx_analogreset[<n>-1:0]
Input
When asserted, resets for TX PMA, TX
clock generation block, and serializer.
Active high, edge sensitive reset signal.
tx_digitalreset[<n>-1:0]
Input
When asserted, resets the digital
components of the TX datapath. Active
high, edge sensitive, asynchronous reset
signal. If your design includes bonded
TX PCS channels, refer to Timing
Constraints for Reset Signals when Using
Bonded PCS Channels for a SDC
constraint you must include in your
design.
rx_analogreset[<n>-1:0]
Input
When asserted, resets the RX CDR,
deserializer. Active high, edge sensitive,
asynchronous reset signal.
rx_digitalreset[<n>-1:0]
Input
When asserted, resets the digital
components of the RX datapath. Active
high, edge sensitive, asynchronous reset
signal.
Parallel data ports
tx_parallel_data[43:0]
Input
PCS TX parallel data, consisting of 4, 11-
bit words. Refer to Table 15-16 for bit
definitions. Refer to Table 15-17 for the
locations of valid words in each
parameter.
rx_parallel_data[63:0]
Output
PCS RX parallel data, consisting of 4, 16-
bit words. Refer to Table 15-18 for bit
definitions. Refer to Table 15-19 for the
locations of valid words in each
parameter .
15-24
Common Interface Ports
UG-01080
2015.01.19
Altera Corporation
Cyclone V Transceiver Native PHY IP Core Overview