Altera Transceiver PHY IP Core - Manual (Page 311)

Standard PCS Parameters for the Native PHY
This section shows the complete datapath and clocking for the Standard PCS and defines the parameters
available in the GUI to enable or disable the individual blocks in the Standard PCS.
Figure 12-3: The Standard PCS Datapath
FPGA
Fabric
Transmitter Standard PCS
Receiver Standard PCS
Transmitter
PMA
Receiver
PMA
TX Phase
Compensa
tion
FIFO
RX Phase
Compensa
tion
FIFO
Byt
e
Serializ
er
Byt
e O
rdering
8B/10B D
ec
oder
Ra
te Ma
tch FIFO
Desk
ew FIFO
8B/10B Enc
oder TX
Bit-Slip
W
or
d A
ligner
Parallel Clock (Recovered)
Serializ
er
Deserializ
er
CDR
tx_serial_da
ta
rx_serial_da
ta
rx_c
or
eclk
in
tx_c
or
eclk
in
Input Reference Clock
from dedicated reference clock pin or fPLL
Clock Divider
Parallel and Serial Clocks Serial Clock
Central/Local Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
CMU / ATX /
fPLL PLL
tx_clkout
rx_clkout
/2
/2
Byt
e
Deserializ
er
Parallel Clock (from Clock Divider)
PRBS
Generator
PRBS
Verifier
UG-01080
2015.01.19
Standard PCS Parameters for the Native PHY 12-13
Stratix V Transceiver Native PHY IP Core Altera Corporation
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