Altera Cyclone II FPGA Starter - Manual (Page 39)

Altera Corporation 5–1
October 2006
5. Using the Development
Board
This chapter provides instructions for using the development board and
describes each of its I/O devices.
Configuring the
Cyclone II FPGA The Cyclone II FPGA Starter Development Board has integrated the
programming circuitry normally found in a USB-Blaster programming
cable, as well as a serial EEPROM chip (EPCS4) that stores configuration
data for the Cyclone II FPGA. This configuration data loads automatically
from the EEPROM chip into the FPGA each time power is applied to the
board.
Using the Quartus II software, it is possible to reprogram the FPGA at any
time, and it is also possible to change the non-volatile data stored in the
serial EEPROM chip. The following sections describe the two ways to
program the FPGA, JTAG programming and Active Serial (AS)
programming.
JTAG Programming
In this method of programming, named after the IEEE standards Joint Test
Action Group, the configuration bit stream downloads directly into the
Cyclone II FPGA through the USB-Blaster circuitry. The FPGA retains this
configuration as long as power is applied to the board; the FPGA loses the
configuration when the power is turned off.
1 For detailed information about the USB-Blaster circuitry, refer to the
Cyclone II FPGA Starter Board schematic found in the
BoardDesignFiles / Schematic
directory in the kit installation
directory.
AS Programming
In the Active Serial programming method, the configuration bit stream
downloads into the Altera EPCS4 serial EEPROM chip. The EEPROM
provides non-volatile storage of the bit stream, retaining the information
even when power to the Cyclone II FPGA Starter board is turned off.
When the board powers up, the configuration data in the EPCS4 device
automatically loads into the Cyclone II FPGA.