Sundance SMT702 - Manual (Page 13)

4.2 Module Description
4.2.1 ADCs
The ADCs are 8-bit parts from National Semiconductor (ADC083000). On the
SMT702, each ADC can achieve up to 3 GSPS, in DDR mode.
Both ADCs are used in the extended mode. For more information, please refer to the
ADC083000 datasheet (National Semiconductor). This implies that they are
configured using a Serial Interface implemented in the FPGA.
The typical Bit Error Rate (BER) of the ADC083000 is 10
-18 .
Each ADC takes a DDR clock, i.e. to achieve 3GSPS, a clock of 1.5Ghz is required.
The ADCs can only work with a DDR clock within the range 500-1500MHz, which
means they can sample at a rate between 1 and 3 GSPS.
Both ADCs are AC-coupled using an RF Transformer.
They have functionalities such as offset and scale adjustments, as well as test
pattern mode. There is also calibration cycle that can be run once the system is in
temperature.
The FPGA is able to synchronise the ADCs so they samples in phase. The FPGA is
able to return the phase shift between ADCA and ADCB to the host application by
sampling their clock with its local clock and phase shifting it with a DCM.
4.2.2
FPGA
4.2.2.1 General Description
The FPGA fitted as standard on the SMT702 is part of the Virtex5 LXT family:
XC5VLX110T. The package used if FFG1136 and the speed grade is -3 (fastest part).
The SMT702 can also receive an FPGA from the Virtex5 FXT family (XC5VFX70T and
XC5VFX100T in the same package).
The FPGA is fitted with a heatsink coupled with a fan to keep it within an
appropriate range of temperature when using the default firmware provided.
Nevertheless the board requires some forced cooling. It is recommended to use a
PXI-1062Q chassis or equivalent from National instrument as it already integrates a
built-in cooling system. Using slot blockers from National Instrument would
improve even more the cooling capacity of the system.
In order to improve the heat dissipation is a system, some slot blockers can be used
(from National Instrument), which redirect the air flow of non-used slots to where it
is needed.
4.2.2.2 Resources used – XC5VLX110T.
Below is a summary (ISE11.4) of the resources used in the FPGA by the default
firmware (Standard SMT702 – XCV5VLX110T FPGA – PXIe option):
Slice Logic Utilization:
Number of Slice Registers: 15,254 out of 69,120 22%
Number used as Flip Flops: 15,244
Number used as Latches: 4
Number used as Latch-thrus: 6
Number of Slice LUTs: 11,699 out of 69,120 16%
Number used as logic: 11,230 out of 69,120 16%
Number using O6 output only: 9,310
Number using O5 output only: 295