Sundance SMT702 - Manual (Page 53)

Setting Bit 9..0 FPGA Core voltage lower threshold
0 The Voltage is coded on 10 bits.
4.3.1.2.35 System Monitor – FPGA Aux Voltages – 0x188 (read).
Offset 0x0400 – System Monitor – FPGA Aux Voltages – 0x188 (read).
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
3 Reserved Maximum Vccaux[9:4]
Default ‘00’ ‘000000’
2 Maximum Vccaux [3:0] Minimum Vccaux [9:6]
Default ‘0000’ ‘0000’
1 Minimum Vccaux [5:0] Current Vccaux [9:8]
Default ‘000000’ ‘00’
0 Current Vccaux [7:0]
Default ‘00000000’
Offset 0x0400 – System Monitor – FPGA Aux Voltages – 0x188 (read).
Setting Bit 29..20 Maximum FPGA Vccaux (measured)
2 The Voltage is coded on 10 bits.
Setting Bit 19..10 Minimum FPGA Vccaux (measured)
1 The Voltage is coded on 10 bits.
Setting Bit 9..0 Current FPGA Vccaux (measured)
0 The Voltage is coded on 10 bits.
4.3.1.2.36 System Monitor – FPGA aux voltage thresholds – 0x188
(write).
Offset 0x0400 – System Monitor – FPGA aux voltage thresholds – 0x188 (write).
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
3 Reserved
Default ‘00000000’
2 Reserved Vccaux upper threshold[9:6]
Default ‘0000’ ‘0000’
1 Vccaux upper threshold[5:0] Vccaux lower
threshold[9:8]
Default ‘000000’ ‘00’
0 Vccaux lower threshold[7:0]
Default ‘00000000’
Offset 0x0400 – System Monitor – FPGA aux voltage thresholds – 0x188 (write).
Setting Bit 19..10 FPGA Aux voltage upper threshold
1 The Voltage is coded on 10 bits.
Setting Bit 9..0 FPGA Aux voltage lower threshold