Sundance SMT702 User Manual
Page 19
Both FPGA and CPLD can be reprogrammed/reconfigured at anytime via JTAG (J8
connector – Using a Xilinx parallel/USB programming cable) but it can cause
problems as it will break the access to the board from the host.
At power up or under a reset on the PXI or PXI Express bus, it takes 140ms for the
FPGA (XC5VLX110T-3) to be fully configured and ready to answer the requests from
the host.
The following table shows the settings that can be used and the start addresses of
the bitstream in the Flash memory.
Position
Switch 2
Position
Switch 1
Bitstream start
address in
flash
Description
ON
ON
0x1800000
(Location 3)
User Bitstream 2
ON
OFF
0x1000000
(Location 2)
User Bitstream 1
OFF
ON
0x0800000
(Location 1)
User bitstream 0
Default
selection
OFF
OFF
0x0000000
(Location 0)
Default
bitstream
Note that the CPLD routes the contents of the flash starting from the location
selected (SW1) until the FPGA indicates that it is configured. Addresses are
incremented by a counter that rolls over to 0 when the maximum address is
reached. For instance, in the case where Location 1 is selected and a corrupted
bitstream is loaded at that location (or if there is no bitstream at that location), the
default bitstream will end up being loaded.
The default bitstream returns ‘DEF’ as firmware version (see register ‘Firmware
Version and Revision numbers).
It is recommended to keep the Switch SW1 so the User bitstream 0 is selected and
store a custom/user bitstream at Location 1 is needed. The card would then boot
from this location. Otherwise the card would boot automatically from the default
firmware (Location 0)
Storing a new bitstream using the SMT6002 first involves erasing the appropriate
sectors before programming them with the bitstream. This is automatically handled
by the SMT6002. Storing a new bitstream at location 1 (User Bitstream 0) will only
require from the user to select the file (.bit for instance) and press the ‘Comit’
button. The advanced tab offers more options such as a full erase or a partial erase
of the flash memory. None of them should be required in normal mode of operation.
Note that a full erase will erase the entire contents of the flash including the default
firmware and that it can take up to 3-4 minutes. The partial erase will erase the User
bitstreams only.
4.2.4
DDR2 Memory
Two banks of DDR2 memory are available on the SMT702, directly connected to the
FPGA. Interfaces are part of the default FPGA design. Each bank is 64-bit wide and
128-Meg deep, so each bank can store up to 1 Giga bytes (or 8-bit ADC samples).
Each memory bank is dedicated to one ADC. Both DDR2 interfaces are independent.
The type of memory fitted on the board can be clocked at a maximum or 333MHz.