Sundance SMT702 - Manual (Page 20)

In order to achieve storage real-time of the ADC samples, the DDR2 interface is
clocked at 250MHz (Default bitstream).
4.2.5
Clock circuitry
An on-board PLL+VCO chip ensures a stable fixed sampling frequency (maximum
rate, i.e. 1500MHz), in order for the board to be used as a digitiser without the need
of external clock signal. The PLL will be able to lock its internal VCO either on the
10MHz PXI reference or the 100MHz PXI express reference or on an external
reference signal. The sampling clock for the converters can be either coming from
the PLL+VCO chip or from an external source. The chip used is a National
Semiconductor part: LMX2531LQ1500.
The selection Internal/External clock is made via a bit in the control register. The
same applies to the selection of the reference clock.
Note that the PLL+VCO chip also has the possibility to output half of the fixed VCO
frequency, i.e. 1500/2=750MHz.