Sundance SMT702 - Manual (Page 32)

Setting Bit 3 Description – Lock Detect (Clock chip)
0 0 The Clock chip hasn’t locked (reference on internal VCO).
1 1 The clock chip has lock. The on-board clock can be used to clock the ADCs.
Setting Bit 4 Description – ADCa DCM Lock Status.
0 0 FPGA DCM not locked.
1 1 FPGA DCM Locked. Normal Mode of Operation.
Setting Bit 5 Description – ADCb DCM Lock Status.
0 0 FPGA DCM not locked.
1 1 FPGA DCM Locked. Normal Mode of Operation.
Setting Bit 6 Description – ADCa programmed.
0 0 ADCa not yet programmed.
1 1 ADCa has been programmed with all registers after an update request has been sent.
Setting Bit 7 Description – ADCb programmed.
0 0 ADCb not yet programmed.
1 1 ADCb has been programmed with all registers after an update request has been sent.
Setting Bit 8 Description – ADCa DCM Busy.
0 0 Normal Mode of Operation.
1 1 The DCM is busy, meaning either in the process of locking or updating its phase shift.
Can be polled when one needs to reprogram phase shifts to make sure it is in the middle
of a cycle.
Setting Bit 9 Description – ADCb DCM Busy.
0 0 Normal Mode of Operation.
1 1 The DCM is busy, meaning either in the process of locking or updating its phase shift.
Can be polled when one needs to reprogram phase shifts to make sure it is not in the
middle of a cycle.
Setting Bit 13 Description – DDR2 phy init done. Memory Bank A.
0 0 A problem occurred or Memory Bank A is kept in reset.
1 1 Normal Mode of Operation.
Setting Bit 14 Description – DDR2 lock status. Memory Bank A.
0 0 A problem occurred or Memory Bank A is kept in reset.
1 1 Normal Mode of Operation.
Setting Bit 15 Description – DDR2 fifo empty. Memory Bank A.
0 0 DDR2 fifo contains samples.
1 1 DDR2 fifo is empty.
Setting Bit 16 Description – IDelay Control Ready. Memory Bank A.
0 0 A problem occurred or Memory Bank A is kept in reset.
1 1 Normal Mode of Operation.
Setting Bit 17 Description – DDR2 Fifo Ready. Memory Bank A.
0 0 Fifo not ready. Data should not be written.
1 1 Normal Mode of Operation.
Setting Bit 18 Description – DDR2 phy init done. Memory Bank B.
0 0 A problem occurred or Memory Bank B is kept in reset.
1 1 Normal Mode of Operation.
Setting Bit 19 Description – DDR2 lock status. Memory Bank B.
0 0 A problem occurred or Memory Bank B is kept in reset.