Sundance SMT702 User Manual
Page 51
There is one bit to set the sign of the phase shit and 8 bit to set the value. The phase
shift range is -255…+255. Once the control word of send, the DCM is being reset
and programmed with the new phase shift. By default, the shift register is set to 0.
4.3.1.2.31
System Monitor – FPGA Die Temperatures – 0x180 (read).
Offset 0x0400 –
System Monitor – FPGA Die Temperatures – 0x180 (read).
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3
Reserved
Maximum Die Temperature[9:4]
Default
‘00’
‘000000’
2
Maximum Die Temperature[3:0]
Minimum Die Temperature[9:6]
Default
‘0000’
‘0000’
1
Minimum Die Temperature[5:0]
Current Die
Temperature[9:8]
Default
‘000000’
‘00’
0
Current Die Temperature[7:0]
Default
‘00000000’
Offset 0x0400 –
System Monitor – FPGA Die Temperatures – 0x180 (read).
Setting
Bit 29..20
Maximum FPGA Die Temperature (measured)
2
The Temperature is coded on 10 bits.
Setting
Bit 19..10
Minimum FPGA Die Temperature (measured)
1
The Temperature is coded on 10 bits.
Setting
Bit 9..0
Current FPGA Die Temperature (measured)
0
The Temperature is coded on 10 bits.
4.3.1.2.32
System Monitor – FPGA Die Temperature thresholds –
0x180 (write).
Offset 0x0400 –
System Monitor – FPGA Die Temperature thresholds – 0x180 (write).
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3
Reserved
Die Temperature OT lower threshold[9:4]
Default
‘00’
‘000000’
2
Die Temperature OT lower threshold[3:0]
Die Temperature upper threshold[9:6]
Default
‘0000’
‘0000’
1
Die Temperature upper threshold[5:0]
Die Temperature lower
threshold[9:8]
Default
‘000000’
‘00’
0
Die Temperature lower threshold[7:0]
Default
‘00000000’
Offset 0x0400 –
System Monitor – FPGA Die Temperature thresholds – 0x180 (write).
Setting
Bit 29..20
Die Temperature OT (Over temperature) lower threshold
2
The Temperature is coded on 10 bits.
Setting
Bit 19..10
Die Temperature upper threshold
1
The Temperature is coded on 10 bits.