Sundance SMT702 - Manual (Page 18)

The parts mentioned above (XC5VLX110T, XC5FX70T, XC5FX100T) are also
footprint compatible with the SXT series: XC5VSX50T and XC5VSX95T. The SXT
series implements a DSP48E core, which if used on the SMT702 may result an
increase of the power consumption. Please contact Sundance if you require details
about the SXT series.
4.2.3
Configuration (CPLD+Flash)
On the SMT702, the FPGA is connected to a CPLD via a serial link. The CPLD is
responsible for controlling read and write operations to and from the Flash memory
and to route data to the FPGA configuration port.
The following diagram show how connections are made on the board between the
CPLD, the Flash memory and the FPGA:
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Figure 5 - Configuration (Flash).
A reset coming from the bus (PXI or PXI Express) triggers a configuration cycle and
the FPGA is configured with the default firmware (stored in factory at location 0).
The on-board Flash memory (256-Mbit part) is big enough to store several versions
of firmware. A switch (SW1) at the back of the board allows the selection among 4
locations (Switches select the bitstream to be booted at power up). Each can contain
up to 8Mbytes of data, which is big enough to store an XC5LX110T bitstream (about
3.8 Mbytes) and some text (comments or description of the firmware version).
The user can store a ‘user’ bitstream at location 1 (see table below) for instance
using the SMT6002 piece of software, also called Flash Utility. The SMT6002 also
allows to add comments (text) above the bitstream in flash memory.
Note that switches don’t have any influence when programming the flash.
This architecture allows the SMT702 to be used as a development platform for
signal processing and algorithms implementation. The function Reboot can be used
from the SMT6002 GUI to boot from any flash location within seconds.