Sundance SMT702 User Manual
Page 3
Table of Contents
1
Introduction ........................................................................................................................ 7
2
Related Documents........................................................................................................... 8
2.1
Referenced Documents ................................................................................................ 8
3
Acronyms, Abbreviations and Definitions................................................................ 8
3.1
Acronyms and Abbreviations ..................................................................................... 8
4
Functional Description .................................................................................................... 9
4.1
General Block Diagram................................................................................................. 9
4.2
Block Diagram - Standard SMT702 (PXIe) ..............................................................10
4.3
Block Diagram – SMT702-HYBRPXI32 (option 32-bit PXI) ..................................11
4.1
Block Diagram – SMT702-CPCI32 (Option 32-bit PCI).........................................12
4.2
Module Description.....................................................................................................13
4.2.1
ADCs..........................................................................................................................13
4.2.2
FPGA ..........................................................................................................................13
4.2.2.1
General Description......................................................................................13
4.2.2.2
Resources used – XC5VLX110T. ................................................................13
4.2.2.3
Resources used – XCV5FX70T....................................................................15
4.2.2.4
Resources used – XCV5FX100T. ................................................................16
4.2.3
Configuration (CPLD+Flash).................................................................................18
4.2.4
DDR2 Memory .........................................................................................................19
4.2.5
Clock circuitry .........................................................................................................20
4.2.6
Data (samples) path / Data capture ...................................................................21
4.2.7
PXI Express Bus .......................................................................................................22
4.2.8
SHB Connector ........................................................................................................24
4.2.9
Power dissipation ...................................................................................................24
4.2.10JTAG ..........................................................................................................................25
4.2.11PXI Express Hybrid Connectors...........................................................................27
4.3
FPGA Design .................................................................................................................28
4.3.1
Control Registers ....................................................................................................28
4.3.1.1
Memory Map...................................................................................................28
4.3.1.2
Register Descriptions ...................................................................................31
4.3.1.2.1
General Control Register – 0x8 (read-only)......................................31
4.3.1.2.2
Set Control Register – 0x10 (write). ...................................................34
4.3.1.2.3
Clear Control Register – 0x20 (write). ...............................................36
4.3.1.2.4
Board Name and Version – 0x24 (read-only). ..................................36
4.3.1.2.5
Firmware Version and Revision Numbers – 0x40 (read-only). ....36
4.3.1.2.6
ADCA (ADC083000) Register 0x1 – Configuration Register –
0x44 (write). ................................................................................................................37
4.3.1.2.7
ADCA (ADC083000) Register 0x2 – Offset Adjust – 0x48 (write
and read). 37
4.3.1.2.8
ADCA (ADC083000) Register 0x3 – Full Scale Voltage Adjust –
0x4C (write and read). ..............................................................................................38
4.3.1.2.9
ADCA (ADC083000) Register 0xD – Extended Clock Phase Adjust
Fine – 0x74 (write and read)....................................................................................38