Sundance SMT702 - Manual (Page 36)

0 0 Normal Mode of Operation
1 1 Resets Xlinks blocks – usually used before starting an acquisition to clear Xlinks FIFOs.
Setting Bit 23 Description – System Monitor Reset
0 0 Normal Mode of Operation
1 1 Keeps System Monitor circuitry in Reset
Note 1: The on-board reference clock is used by the on-board clock generator, which
can only take reference clock within the range 5-80MHz. Bit13 must be set for all
reference reaching the chip above 80MHz.
4.3.1.2.3 Clear Control Register – 0x20 (write).
Same as Set Control Register (0x10) but used to clear individual register bits.
4.3.1.2.4 Board Name and Version – 0x24 (read-only).
Offset 0x0400 - Reset Register – 0x24 (read-only)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
3 Board Name (MSB)
2 Board Name (LSB)
1 FPGA Type
0 FPGA Type PCB Revision
Offset 0x0400 - Reset Register – 0x24 (read-only)
Setting Bit 3:0 Description – PCB Revision
Return a number coded in binary on 4 bits.
Setting Bit 11:4 Description – FPGA Type
Return 110 for an LX110T FPGA, 070 for and FX70T FPGA, 100 for and FX100T FPGA.
Setting Bit 31:12 Description – Board name
Returns 0702, as an hexadecimal value.
4.3.1.2.5 Firmware Version and Revision Numbers – 0x40 (read-
only).
Offset 0x0400 - Reset Register – 0x40 (read-only)
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
3 Firmware Version Number (MSB)
2 Firmware Version Number (LSB)
1 Firmware Revision Number (MSB)
0 Firmware Revision Number (LSB)
Offset 0x0400 - Reset Register – 0x40 (read-only)
Setting Bit 15:0 Description – Firmware Revision
Return a number coded in binary on 16 bits.
Setting Bit 31:16 Description – Firmware Version
Returns 0DEF (hexadecimal value) for the default firmware.