FUJITSU MHZ2250BJ User Manual
Page 162
Interface
Table 5.32 DEVICE CONFIGURATION IDENTIFY data structure (2/2)
Word Value
Content
8
X '0015'
Serial-ATA command set/function
Bit 4:
1 = Software Settings Preservation supported
Bit 1:
1 = Non-zero buffer offsets in DMA Setup FIS
supported
→ Reflected in IDENTIFY information "Word 76 to 79".
Bits 15-5: Reserved
Bit 3:
1 = Asynchronous Notification supported
Bit 2:
1 = Interface power management supported
Bit 0:
1 = Native command queuing supported
9
X '0000'
Reserved for Serial-ATA
10 to 20
X '0000'
Reserved
21 X
'2000'
(X '2800' *1)
Bits 15-14: Reserved
Bit 13:
Write uncorrectable is supported.
Bit 12:
Reserved
Bit 11:
Freefall Control feature set is supported. *1
Bit 10-0: Reserved
22 to 254
X '0000'
Reserved
255
X 'xxA5'
Bits 15-8: Check sum code (This is obtained by calculating the
sum of all upper bytes and lower bytes in WORD 0 to
256 and the byte consisting of bits 7 to 0 in WORD
255, and then calculating the two's complement of the
lowest byte of that sum.)
Bits 7-0:
0xA5 (signature)
*1: Optional
5-88
C141-E280