Motorola MVME1X7P - Manual (Page 110)

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VMEchip2
2
The interrupt handler provides all logic necessary to identify and handle all
local interrupts as well as VMEbus interrupts. When a local interrupt is
acknowledged, a unique vector is provided by the chip. Edge-sensitive
interrupters are not cleared during the interrupt acknowledge cycle and
must by reset by software as required. If the interrupt source is the
VMEbus, the interrupt handler instructs the VMEbus master to execute a
VMEbus IACK cycle to obtain the vector from the VMEbus interrupter.
The chip connects to all signals that a VMEbus handler is required to drive
and monitor. On the local bus, the interrupt handler is designed to comply
with the interrupt handling signaling protocol of the MC680x0
microprocessor.
Global Control and Status Registers
The VMEchip2 ASIC includes a set of registers that are accessible from
both the VMEbus and the local bus. These registers are provided to aid in
interprocessor communications over the VMEbus. These registers are
fully described in a later section.
LCSR Programming Model
This section defines the programming model for the Local Control and
Status registers (LCSR) in the VMEchip2 ASIC. The local bus map
decoder for the LCSR is included in the VMEchip2. The base address of
the LCSR is $FFF40000 and the registers are 32 bits wide. Single-byte,
double-byte, and quad-byte read operations are permitted, but single-byte
and double-byte write operations are not. Single- and double-byte write
operations return a TEA signal to the local bus. Read-modify-write
operations should be used to modify a byte or a two-byte of a register.
Each register definition includes a table with five lines:
1. The base address of the register and the number of bits defined in
the table.
2. The bits defined by this table.
3. The name of the register or the name of the bits in the register.