Motorola MVME1X7P User Manual

Page 309

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IN-7

I

N
D

E
X

local bus interrupter registers

I/O Control register 1

2-96

I/O Control register 2

2-97

I/O Control register 3

2-97

Interrupt Level register 4 (bits 0-7)

2-95

Miscellaneous Control register

2-98

Status register (bits 16-23)

2-78

Status register (bits 24-31)

2-77

Vector Base register

2-95

local bus master

2-9

VMEbus and

2-10

local bus slave (VMEbus master) registers

Address Translation Address Register 4

2-42

Address Translation Select Register 4

2-42

Attribute Register 1

2-46

Attribute Register 2

2-45

Attribute Register 3

2-44

Attribute Register 4

2-43

Ending Address Register 1

2-39

Ending Address Register 2

2-40

Ending Address Register 3

2-41

Ending Address Register 4

2-41

Starting Address Register 1

2-40

Starting Address Register 2

2-40

Starting Address Register 3

2-41

Starting Address Register 4

2-42

local bus slave, composition of

2-4

local bus timer

VMEchip2 ASIC

2-18

local control and status segisters (LCSRs),

VMEbus

2-7

local I/O devices memory map

1-22

local reset driver, VMEbus

2-18

local reset, VMEbus

2-18

local SCSI ID

1-45

local-bus-to-VMEbus

Enable Control register

2-49

I/O Control register

2-50

interface

1-18

interface, VMEchip2

2-4

map decoders, programming

2-37

requester

2-7

requester register, programming

2-51

location monitor

interrupters, VMEbus

2-19

status register (VMEchip2 ASIC)

2-101

location monitors LM0-LM3 (VMEchip2

ASIC)

2-100

LVFAIR bit (VMEchip2 ASIC)

2-8

M

M48T58 BBRAM, TOD Clock memory map

1-42

manual strobe control

3-45

map decoders

2-37

GCSR

1-46

SDRAM

1-11

VMEbus interface

1-46

VMEchip2 ASIC

2-4

,

2-6

,

2-9

master interrupt enable (MIEN) bit

2-74

,

2-96

master interrupt enable (PCCchip2 ASIC)

3-15

MC68040

bus master support for 82596C

3-4

MPU

1-7

MC68060

MPU

1-7

MC680x0

indivisible RMW memory accesses

1-52

MOVE16 access

3-10

normal access

3-10

MCECC chip Memory Controller ASIC

1-3

MCECC internal register memory map

1-34

MCECC sector

arbitration process

4-9

Base Address register

4-15

BCLK Frequency register

4-16

chip defaults

4-9

Chip Prescaler counter

4-21

Data Control register

4-17

Defaults register 1

4-30

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