Motorola MVME1X7P User Manual

Page 305

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IN-3

I

N
D

E
X

clear-on-compare mode, VMEchip2 counters

2-15

clocks for VMEchip2 counters and timers

2-67

command chaining mode, VMEchip2

DMAC

2-12

,

2-52

command packets, DMAC

2-52

compatibility, backward

1-2

connection diagrams

printer and serial port

B-1

transition module

B-1

Control and Status registers (CSRs),

PCCchip2 ASIC

3-11

memory map

3-12

counter enable

tick timer 1

3-23

tick timer 2

3-22

cycle types, MCECC sector

4-5

D

data access cycles, VMEbus

2-33

,

2-36

data bus structure

1-7

data sheets, sources of

C-2

data transfer capabilities

local-bus-to-VMEbus interface

2-4

VMEbus-to-local-bus interface

2-9

VMEchip2 DMAC

2-11

data transfer size, VMEchip2 DMAC

2-11

data transfers, DMA (VMEchip2 ASIC)

2-52

data transfers, VMEbus

2-43

,

2-44

DCE connections (serial ports)

B-1

debugging packages

C-1

decimal number, symbol for

xxiii

decoders

programmable

2-4

VMEchip2

2-26

devices, normal address range

1-20

DFAIR bit

2-14

differences from previous boards

A-1

direct mode

DMAC

2-51

PCCchip2 ASIC

3-7

DMA

and serial interface

1-14

transfers, no-address-increment

2-12

DMA Controller (DMAC), VMEchip2 ASIC

2-10

,

2-51

DMAC

command packets

2-52

interrupter, VMEbus

2-19

LTO error

1-58

offboard error

1-58

parity error

1-57

TEA, cause unidentified

1-59

VMEbus error

1-57

VMEbus requester

2-13

DMAC registers (VMEchip2 ASIC)

DMAC byte counter

2-60

DMAC Control register 1 (bits 0-7)

2-55

DMAC Control register 2 (bits 0-7)

2-58

DMAC Control register 2 (bits 8-15)

2-57

DMAC local bus address counter

2-59

DMAC Status register

2-63

DMAC VMEbus address counter

2-60

Local-Bus-to-VMEbus Requester

Control register

2-54

MPU Status and DMA Interrupt Count

register

2-62

PROM Decoder, SRAM and DMA

Control register

2-53

table address counter

2-60

VMEbus Interrupter Control register

2-61

VMEbus Interrupter Vector register

2-62

double bit error

4-6

DRAM

map decoder

1-11

specifications

1-3

DS1210S device

1-10

DTACK* signal (VMEchip2 ASIC)

2-9

DTE connections (serial ports)

B-1

dump, performing

3-3

DWB bit (VMEchip2 LCSR)

2-8

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