Motorola MVME1X7P - Manual (Page 146)

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VMEchip2
2
always requests at the old level until it becomes bus
master and the new level takes effect. If the VMEchip2 is
bus master when the level is changed, the new level does
not take effect until the bus has been released and re-
requested at the old level. The requester always requests
the VMEbus at level 3 the first time following a
SYSRESET.
0 VMEbus request level 0
1 VMEbus request level 1
2 VMEbus request level 2
3 VMEbus request level 3
DRELM These bits define the VMEbus release mode for the
DMAC requester. The DMAC always releases the bus
when the FIFO is full (VMEbus to local bus) or empty
(local bus to VMEbus).
0 Release when the time on timer has expired
and a BRx
∗
signal is active on the VMEbus.
1 Release when the time on timer has expired.
2 Release when a BRx
∗
signal is active on the
VMEbus.
3 Release when a BRx
∗
signal is active on the
VMEbus or the time on timer has expired.
DFAIR When this bit is high, the DMAC requester operates in fair
mode. It waits until its request level is inactive before
requesting the VMEbus. When this bit is low, the DMAC
requester does not operate in fair mode.
DTBL The DMAC operates in direct mode when this bit is low,
and it operates in command chaining mode when this bit
is high.
DEN The DMAC is enabled when this bit is set high. This bit
always reads 0.
DHALT When this bit is high, the DMAC halts at the end of a
command when the DMAC is operating in command
chaining mode. When this bit is low, the DMAC executes
the next command in the list.