Motorola MVME1X7P - Manual (Page 266)

4-18 Computer Group Literature Center Web Site
MCECC Functions
4
The writing of checkbits causes the MCECC sector to
perform a read-modify-write to DRAM. If the location to
which check bits are being written has a single- or double-
bit error, data in the location may be altered by the write
checkbits operation. To avoid this, it is recommended that
the DERC bit also be set while the RWCKB bit is set. A
suggested sequence for performing read-write checkbits
is as follows:
1. Stop all scrub operations by clearing all of the STON bits and setting
all of the STOFF bits in the Scrub Time On/Time Off register.
2. Set the DERC and RWCKB bits in the Data Control register.
3. Perform the desired read and/or write checkbit operations.
4. Clear the DERC and RWCKB bits in the Data Control register.
5. Perform the desired testing related to the location/locations that
have had their checkbits altered.
6. Allow the scrubber to proceed by restoring the STON and STOFF
bits to their original state.
ZFILL ZERO FILL memory, when set, forces all zeros to be
written to the DRAM during any kind of write cycle or
scrub cycle. It is intended for use with the zero-fill
function (refer to the section on
Initialization at the end of
this chapter). This bit should be cleared for normal system
operation.
When ZFILL is set, the read portion of a scrub cycle is
suppressed and writes of all zeros are executed.
DERC DISABLE ERROR CORRECTION, when set to 1,
disables single-bit error correction by the Petra MCECC
sector. Specifically, data read from the DRAM array is
presented to the local MC680x0 data bus unaltered. Less-
than-line write data performs a read-modify-write without
correcting single-bit errors that may occur on the read
portion of the read-modify-write. Note that DERC does
not affect the generation of check bits. DERC should be