Motorola MVME1X7P - Manual (Page 222)

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PCCchip2
3
General Purpose Input Interrupt Control Register
IL2-IL0 These three bits select the interrupt level for the general
purpose input/output (GPIO) pin. Level 0 does not
generate an interrupt.
ICLR In edge-sensitive mode, writing a logic 1 to this bit clears
the INT status bit. This bit has no function in level-
sensitive mode. This bit is always read as zero.
IEN When this bit is high, the interrupt is enabled. The
interrupt is disabled when this bit is low.
INT When this bit is high, a general purpose input interrupt is
being generated at the level programmed in IL2-IL0 (if
nonzero).
E/L* When this bit is high, the interrupt is edge-sensitive. The
interrupt is level-sensitive when this bit is low.
PLTY When this bit is low, the interrupt is activated by either a
rising edge on the GPIO pin or a high level on the GPIO
pin (depending on the E/L* bit).
When this bit is high, the interrupt is activated by either a
falling edge on the GPIO pin or a low level of the GPIO
pin (depending on the E/L* bit).
Note that if this bit is changed while the E/L* bit is set (or
is being set), a GPIO interrupt may be generated. This can
be avoided by setting the ICLR bit during write cycles that
change the E/L* bit.
ADR/SIZ $FFF42018 (8 bits)
BIT 31 30 29 28 27 26 25 24
NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0
OPER R/W R/W R R/W C R/W R/W R/W
RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL