Motorola MVME1X7P - Manual (Page 228)

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PCCchip2
3
SCC Receive Interrupt Control Register
IL2-IL0 Interrupt Request Level. These three bits select the
interrupt level for SCC Receive Interrupt. Level 0 does
not generate an interrupt.
AVEC When this bit is high, the PCCchip2 supplies the interrupt
vector to the MPU during an IACK for SCC receive
interrupt. When this bit is low, the PCCchip2 obtains the
vector from the SCC and passes it to the MPU. The use of
the AVEC mode is not recommended.
IEN Interrupt Enable. When this bit is high, the interrupt is
enabled. The interrupt is disabled when this bit is low.
IRQ Interrupt Status. This status bit reflects the state of the
SCC-IRQ3 pin of the CD2401 (qualified by the IEN bit).
When this bit is high, an SCC receive interrupt is being
generated at the level programmed in IL2-IL0 (if
nonzero). This status bit does not need to be cleared,
because it is not edge-sensitive.
SC1-SC0 Snoop Control. These control bits determine the value that
the PCCchip2 drives onto the local MC68040 bus SC1
and SC0 pins, when the CL-CD2401(SCC) performs
DMA accesses. During SCC DMA, when bit SC0 is 0,
Local Bus pin SC0 is low, and when bit SC0 is 1, pin SC0
is high. The same relationship holds true for bit and pin
SC1. See the M68040 and MC68060 user’s manuals for
details on how it uses the Snoop Control signals.
Note On the MVME177P, which uses only SC1, the SC0 bit must
be 0.
ADR/SIZ $FFF4201F (8 bits)
BIT 7 6 5 4 3 2 1 0
NAME SC1 SC0 IRQ IEN AVEC IL2 IL1 IL0
OPER R/W R/W R R/W R/W R/W R/W R/W
RESET 0 PL 0 PL X 0 PL 0 PL 0 PL 0 PL 0 PL