Motorola MVME1X7P - Manual (Page 227)

Programming Model
http://www.motorola.com/computer/literature 3-29
3
SCC Transmit Interrupt Control Register
IL2-IL0 Interrupt Request Level. These three bits select the
interrupt level for SCC Transmit Interrupt. Level 0 does
not generate an interrupt.
AVEC When this bit is high, the PCCchip2 supplies the interrupt
vector to the MPU during an IACK for SCC transmit
interrupt. When this bit is low, the PCCchip2 obtains the
vector from the SCC and passes it to the MPU. The use of
the AVEC mode is not recommended.
IEN Interrupt Enable. When this bit is high, the interrupt is
enabled. The interrupt is disabled when this bit is low.
IRQ Interrupt Status. This status bit reflects the state of the
SCC-IRQ2 pin of the CD2401 (qualified by the IEN bit).
When this bit is high, an SCC Transmit interrupt is being
generated at the level programmed in IL2-IL0 (if
nonzero). This status bit does not need to be cleared,
because it is not edge-sensitive.
ADR/SIZ $FFF4201E (8 bits)
BIT 15 14 13 12 11 10 9 8
NAME IRQ IEN AVEC IL2 IL1 IL0
OPER R R R R/W R/W R/W R/W R/W
RESET 0 0 X 0 PL 0 PL 0 PL 0 PL 0 PL