Samsung S3F401F - Manual (Page 107)

INVERTER MOTOR CONTROLLER (IMC) S3F401F_UM_REV1.00
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Inverter Motor Control Register 0 (Continued) IMCON0 (0x000) Access: Read/Write
SYNCSEL Synchronous Write Time Selection Field
00 = Synchronous write at counter matches ZERO and TOPCMP.
01 = Synchronous write at counter matches ZERO.
10 = Synchronous write at counter matches TOPCMP.
11 = Should not be used.
DBGEN Debug Enable Bit
0 = IMC is halted during processor debug mode.
1 = IMC is not halted during processor debug mode.
NOTES:
1. If WMODE is equal to 1 and NUMSKIP is equal to 0, the update of compare registers is like below picture. Because
NUMSKIP is 0, the written compare registers are updated every TOPCMP and 0 time.
2. If IMEN is equal to 0, all PWM output (PWMxU/Dx) goes to High-Z state.
1) SYNCSEL = 00
TOPCMP