Masked interrupt status register – Samsung S3F401F User Manual
Page 223
SSP
S3F401F_UM_REV1.00
10-22
Masked Interrupt Status Register
SSPMIS (0x01C)
Access: Read Only
31 30 29 28 27 26 25 24
−
−
−
−
−
−
−
−
R-0 R-0
R-0
R-0
R-0
R-0
R-0
R-0
23 22 21 20 19 18 17 16
−
−
−
−
−
−
−
−
R-0 R-0
R-0
R-0
R-0
R-0
R-0
R-0
15 14
13
12
11
10
9 8
−
−
−
−
−
−
−
−
R-0 R-0
R-0
R-0
R-0
R-0
R-0
R-0
7 6
5
4
3
2
1
0
−
−
−
−
TXRIS
RXRIS
RTRIS
RORRIS
R-0 R-0
R-0
R-0
R-0
R-0
R-0
R-0
W: Write
R: Read
-0: 0 After reset
-1: 1 After reset
-U: Undefined after reset
RORRIS
Gives the receive over run masked interrupt status(after masking) of the SSPRORINTR
interrupt
RTRIS
Gives the receive timeout masked interrupt state(after masking) of the SSPRTINTR interrupt
RXRIS
Gives the receive FIFO masked interrupt state(after masking) of the SSPRXINTR interrupt
TXRIS
Gives the transmit FIFO masked interrupt state(after masking) of the SSPTXINTR interrupt
NOTE
On a read this register gives the current masked status value of the corresponding interrupt. A write has no
effect.