Receive status/error clear register – Samsung S3F401F User Manual
Page 255

S3F401F_UM_REV1.00
UART
12-17
Receive Status/Error Clear Register
UARTRSR (0x004)
Access: Read/Write
31 30 29 28 27 26 25 24
−
−
−
−
−
−
−
−
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
−
−
−
−
−
−
−
−
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
−
−
−
−
−
−
−
−
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
−
−
−
−
OE_RSR
BE_RSR
PE_RSR
FE_RSR
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W: Write
R: Read
-0: 0 After reset
-1: 1 After reset
-U: Undefined after reset
FE_RSR
Frame Error
1: indicates that the received character did not have a valid stop bit (a valid stop bit is 1.)
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the FIFO.
PE_RSR
Parity Error
1: indicates that the parity of the received data character does not match the parity selected as
defined by bits 2 and 7 of the UARTLCR_H register.
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the FIFO.
BE_RSR
Break Error
1: if a break condition was detected, indicating that the received data input was held LOW for
longer than a full-word transmission time (defined as start, data, parity and sop bits.)
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the top of the FIFO. When a break
occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the
receive data input goes to a 1 (marking state), and the next valid start bit is received.
OE_RSR
Overrun Error
1: if data is received and the receive FIFO is already full. This bit is cleared to 0 by a write to
UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full,
only the contents of the shift register are overwritten. The CPU must now read the data in order
to empty the FIFO.
Bit[7:0] A write to this register clears the framing, parity, break, and overrun errors. The data
value is not important.