Samsung S3F401F - Manual (Page 193)

S3F401F_UM_REV1.00 POWER MANAGEMENT
9-5
Divider
P
Fin
M[7:0]
S[1:0]
PWRDN
PFD
Divider
M
P[5:0]
Fvco
PUMP
VCO
Divider
S
Fref
Fpllo
Loop Filter
R
1200pF
C
Internal
PLLCAP
External
Figure 9-3. PLL (Phase-Locked Loop) Block Diagram
2.2 PLL VALUE CHANGE STEPS
If the PLL setting needs to be changed when Fpllo is used as MCLK/PCLK, the PLL transition noise may be asserted
to CPU core. So the PLL configuration has to be changed in SLOW mode. Do the following steps to change the PLL
configuration.
1. Set CLKSRC = EXTCLK
2. Set PMS value of PLL
3. Wait for at least 300us.
4. Set CLKSRC = PLL output
2.3 CAPACITOR FOR PLL LOOP FILTER
A 1200pF (same or slightly bigger) capacitor is connected between PLLCAP pin and Vss. This capacitor will operate
as a PLL loop filter.
PLLCAP
1200pF
Figure 9-4. Capacitor for PLL Loop Filter