Samsung S3F401F - Manual (Page 262)

UART S3F401F_UM_REV1.00
12-24
UART Line Control Clock Register UARTLCR_H (0x02C) Access: Read/Write
31 30 29 28 27 26 25 24
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
SPS WLEN[6:5] FEN STP2 EPS PEN BRK
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
BRK Send Break
If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing
transmission of the current character. For the proper execution of the break command, the
software must set this bit for at least two complete frames.
For normal use, this bit must be cleared to 0.
PEN Parity Enable
The parity mode specifies how parity generation and checking are to be performed during UART
transmit and receive operations.
1: parity checking and generation is enabled, else parity is disabled and no parity bit added to the
data frame.
EPS Even Parity Select
1: even parity generation and checking is performed during transmission and reception, which
checks for an even number of 1s in data and parity bits. When cleared to 0 then odd parity is
performed which checks for an odd number of 1s. This bit has no effect when parity is disabled
by parity enable(bit 1) being cleared to 0.
STP2 Two Stop Bits Select
The number of stop bits specifies how many stop bits are to be used to signal end-of-frame.
0 = One stop bit per frame
1 = Two stop bit per frame
1: two stop bits are transmitted at the end of the frame. The receive logic does not check for two
stop bits being received.