Samsung S3F401F User Manual
Page 231
S3F401F_UM_REV1.00
TIMER
11-7
TCLK
TPDAT
9
INT_OVERFLOW
TnPWM
INT_MATCH
TDAT
TCNT
0
1
2
8
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
0
1
Period
2
Figure 11-6. PWM Signal Generation Diagram
PWM duty can be calculated with TPDAT and TDAT register value. In PWM mode, TPDAT is greater than TDAT. So
to generate 100% duty, you should set the same value in TPDAT and TDAT. For example figure 11-6, TDAT sets
8*TCK and TPDAT sets 9*TCLK.
PWM Duty = (TDAT / (TPDAT+1))* 100% when the value of TDAT register is not equal that of TPDAT.
PWM Duty = 100%
when the value of TDAT register is the same of TPDAT.
The start level is decided by TCON.1 bit. In case of ‘0’ (reset value), PWM signal starts form High level. The other
case, TCON.1=1, PWM signal starts from Low level.
In PWM mode, the value of TPDAT and TDAT register is updated at the time that happen match and overflow
interrupt. In other modes, Interval mode, Capture mode and Match & Overflow mode, that value is updated with
match interrupt.
In this mode, a match signal should be generated when the counter value is identical to the written to the timer data
register. However,
PWM have two operating mode, one-shot mode and continuous mode. In one-shot mode, when one pulse is
signaled through output port, a match interrupt occurs. After that, if timer becomes from enable to disable, timer
generate match and overflow interrupt repeatedly.