Samsung S3F401F - Manual (Page 41)

S3F401F_UM_REV1.00 BASIC TIMER & WDT
3-1
3
BASIC TIMER & WATCHDOG TIMER
1. OVERVIEW
Basic Timer/Watch-Dog Timer can be used to resume the controller operation when it is disturbed due to noise,
system error, or other kinds of malfunction.
To have a configuration on Watch-dog Timer, the overflow signal from 8-bit Basic Timer should be fed to the clock
input of 3-bit Watch-dog Timer as shown in below figure. User can enable or disable the Watch-dog Timer by
software, i.e., by controlling the configuration in BTCON register. If users do not want to use the configuration of
Watch-dog Timer, the 8-bit Basic Timer can only be used as a normal interval timer to request the interrupt service.
Also, it works to signal the end of the required oscillation interval after a reset or Stop mode release.
For example, the Basic Timer can give the overflow signal to necessary logic blocks after a reset or release from
Stop mode. In this case, the overflow signal from Basic Timer can guarantee the necessary time delay for stable
clock from external oscillator circuit.
.
nRESET
After releasing from RESET or STOP mode,
when BTCNT.4 is set , CPU Start.
INTMSK
OVF
INT_BT
BTCON.15-.8: WDTE
RESET or STOP
Clear
Clear
BTCNT.7-.0: BCV
8-Bit Basic Counter
BTCNT.11-.8: WCV
3-Bit WDTimer Counter
BTCON.3-.2: CS
BTCON.0 : WDTC RESET or STOP or IDLE
BTCON.1: BTC
Fin
CLK DIV
Fin/2 12
Fin/2 10
Fin/2 6
Fin/2 5
INTPND
4,6 or 8MHz
Figure 3-1. Basic Timer Block Diagram
NOTE: In the clock fail mode, the clock source of basic timer is internal oscillator.