Samsung S3F401F - Manual (Page 233)

S3F401F_UM_REV1.00 TIMER
11-9
Timer Control Register TCON (0x000) Access: Read/Write
31 30 29 28 27 26 25 24
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
− − − − − −
T_CLKFTON T_CAPFTON
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
TEN CL OMS[5:3] ICS IVT DBGEN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
DBGEN Debug Enable Bit
0 = Timer is halted during processor debug mode.
1 = Timer is not halted during processor debug mode.
IVT Phase Inverting Selection for PWMn Bit
0 = Normal Phase
1 = Invert Phase
ICS Timer Input Clock Selection Bit
0 = Internal Clock
1 = External Clock
OMS Timer Operating Mode Selection Field
000 = Interval mode operation
001 = Match & overflow mode operation
010 = PWM mode operation (Continuous mode)
100 = Capture on falling edge of TxCAP
101 = Capture on rising edge of TxCAP
110 = Capture on both edges of TxCAP
111 = PWM mode operation (One shot mode)
CL Timer Counter Clear Bit
0 = No effect
1 = Clearing the counter register
Note: This bit is auto-clear bit.