Samsung S3F401F - Manual (Page 24)

PRODUCT OVERVIEW S3F401F_UM_REV1.00
1-10
Table 1-2. S3F401F Pin Descriptions (Continued)
Module Pin Name Description I/O
SDAT Serial Data pin (Output when reading, Input when writing)
Input & Push-pull output port can be assigned. I/O TOOL Program
SCLK Serial Clock, input only
Writer speed : Max 250kHz, Read speed: Max 3MHz
I
nTRST nTRST (TAP Controller Reset) can reset the TAP controller at
power-up. A 200K pull-up resistor is connected to nTRST pin,
internally. If the debugger is not used, nTRST pin should be
"Low" level or low active pulse should be applied before CPU
running. For example, nRESET signal can be tied with
nTRST. I
TMS TMS (TAP Controller Mode Select) can control the sequence
of the state diagram of TAP controller. A 200K pull-up resistor
is connected to TMS pin, internally. I
TCK TCK (TAP Controller Clock) can provide the clock input for the
JTAG logic. This pin is floating pin. When reduced the current
and not debugging mode, connect to the VDD with pull-up
resistor. I
RTCK RTCK (TAP Controller Retiming Clock) can provide the clock
output for the JTAG logic.
Connect to GND through a 33pF capacitor.
I
TDI TDI (TAP Controller Data Input) is the serial input for JTAG
port. A 200K pull-up resistor is connected to TDI pin,
internally. I
JTAG
TDO TDO (TAP Controller Data Output) is the serial output for
JTAG port. O
PWM[1:0]U[2:0] PWM output for inverter motor O
PWM[1:0]D[2:0] PWM output for inverter motor O
INVERTER
MOTOR
CONTROLLER
PWM[1:0]OFF Input pin for PWM output off I
ENCODER PHASEA[1:0] Phase A input pin I
PHASEB[1:0] Phase B input pin I
PHASEZ[1:0] Phase Z input pin I
P0.[18:0] General input/output port 0 I/O
P1.[30:0] General input/output port 1 I/O
GERNAL
PURPOSE
PORT
P2.[14:0] General input/output port 2 I/O