Samsung S3F401F - Manual (Page 47)

S3F401F_UM_REV1.00 BASIC TIMER & WDT
3-7
Basic Timer Control Register BTCON (0x000) Access: Read/Write
31 30 29 28 27 26 25 24
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
WDTE[15:8]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
− − − −
CS[3:2] BTC WDTC
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
WDTC Watch-Dog Timer Clear Bit
0 = No effect
1 = Watch-Dog Timer Counter will be cleared to all zero.
Note: This bit is auto-clear bit.
BTC Basic Timer Clear Bit
0 = No effect
1 = Basic Timer Counter will be cleared to all zero.
Note: This bit is auto-clear bit.
CS Clock Source Select Field
00 = Fin / 2^12
01 = Fin / 2^10
10 = Fin / 2^6
11 = Fin / 2^5
WDTE Watchdog Timer Enable Bit
0xA5 = Watchdog Timer Counter will be stopped
Others = Watchdog Timer Counter can enable, and make a system reset when overflow
DBGEN Debug Enable Bit
0 = BT/WDT is halted during processor debug mode.
1 = BT/WDT is not halted during processor debug mode.