Tclk – Samsung S3F401F User Manual
Page 226
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TIMER
S3F401F_UM_REV1.00
11-2
INTPND
INTMASK
INT_TOFn
NOTE1
:The counter clear by match is occurred only in the interval mode.
Timer n Buffer Register
TCON.5-.3:
OMS
16-bit Comparator
TDAT.7-.0:
DATA
Timer Data Register
Data Bus
INT_TMCn
Data Bus
TCNT.15-.0:
CV
16-bit Up Counter
Match signal
TnCL
TnOVF
Match
(NOTE1)
TCON.5-.3:
OMS
TnCAP
TCON.1:
IVT
TnPWM
INTPND
INTMASK
TCON.6:
CL
Clear
TCON.7:
TEN
TCON.2:
ICS
TPRE.7-.0:
PRESCALE
TnCLK
PCLK
TCON.6:
CL
Clear
TCLK
< Timer Clock Generation Part >
TCLK
Figure 11-1. 16-Bit Timer Block Diagram
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